Japanese Patent Laid-Open No. 2002-4098, Japanese Patent Laid-Open No. 330336/1994, Japanese Patent Laid-Open No. 2003-13248, “evaluation of Lead-free Solder Balls Produced by Uniform Droplet Spray Method” Hitachi Metals Technical Review, Vol. 18 (2002), p. 43, and “Development of Highly Reliable Sn—Ag Lead-Free Solder Alloy” Toyota Central R&D Labs. R&D Review, Vol. 35, No. 2 (2000), p. 39 are background of the invention.
Of multi-layer wiring boards to be used for connecting chips such as ICs or LSIS, a wiring board called an organic package board has a wiring laminate portion in which dielectric layers of polymeric material and conductor layers have been laminated alternately. A plurality of metal terminal pads for flip-chip connection or mother board connection (for example, using BGA or PGA) are disposed on a first main surface formed out of one of the dielectric layers of the wiring laminate portion These metal terminal pads are conductively connected to inner conductor layers disposed in the wiring laminate portion, through vias. The inner conductor layers and the vias are generally formed out of Cu-based metal having a high conductivity. Each metal terminal pad has a body portion to be connected to the inner conductor layers and the vias, and the body portion is also formed as a Cu-plated layer. Solder will be in contact with each metal terminal pad for connection to a chip or a mother board. Thus, Au-plating is performed on the metal terminal pad in order to improve bonding power and wettability with the solder
However, it cannot be said that the Cu-plated layer forming the body portion of each metal terminal pad is so high in corrosion resistance. Therefore, when the surface is covered with an oxide layer or the like, there is a possibility that the adhesion of the Au-plated layer deteriorates. In addition, Cu wells up by diffusion from the Cu-plated layer to the surface of the Au-plated layer due to heating during reflow or the like so that the surface of the Au-plated layer is covered with an oxide layer of Cu. Thus, there is a problem that the solder wettability or the solder bonding property is impaired on a large scale. In addition, an Sn component of the solder diffuses into the Cu-plated layer through the Au-plated layer, so as to produce a brittle Cu—SN-based intermetallic compound layer easily. Particularly when thermal stress or the like is applied, there is a problem that peeling is apt to occur between the Cu—SN-based intermetallic compound layer and the base portion of the Cu-plated layer. Particularly in a metal terminal pad for BGA (Ball Grid Array) for connecting the board to a mother board through a solder ball, the pad area is so large that thermal stress is also applied thereto easily. Thus, the aforementioned problem is apt to occur.
Therefore, the following pad structure is adopted broadly. That is, a Cu-plated layer is formed, an Ni-plated layer having good adhesion to Cu is then formed as a barrier metal layer on the Cu-plated layer, and an Au-plated layer is formed on the Ni-plated layer. To form the Ni-plated layer, there are two kinds of methods. One is a method using electrolytic Ni-plating, and the other is a method using electroless Ni-plating (Japanese Patent Laid-Open No. 2002-4098). However, in a pad forming process using electrolytic Ni-plating, a vermiculated plating tie bar to be connected to pads has to be formed on a dielectric layer surface (pad formation surface) on which the pads will be formed. In this method, a space to which the plating tie bar is inserted must be secured between the pads. As a result, the interval with which the pads are arrayed cannot be reduced to be shorter than a fixed value. Thus, there is a problem that the board area is apt to be increased, and restriction in design becomes very severe. On the other hand, when electroless Ni-plating is used, such a plating tie bar is unnecessary. Therefore, such a problem does not occur. In addition, there is an advantage that an Ni-plated layer can be formed easily by immersion in a plating solution, even on a plurality of pads isolated from one another on a dielectric layer.